Programmable logic devices (“PLDs”), such as complex programmable logic devices (“CPLDs”) and field-programmable gate arrays (“FPGAs”) have a fabric of logic devices (e.g. flip-flops in configurable logic blocks) interconnected with a switch matrix of conductive signal lines (also known as interconnect lines) and programmable interconnect points (“PIPs”). The switch matrix typically provides many different selectable paths (commonly called line segments or routes) between an input (e.g. a first flip-flop) and an output (e.g. a second flip-flop). When the user configures the PLD to perform a selected logic function (i.e. programs the PLD), the line segments are defined (routed) through the switch matrix.
A PIP is basically a programmable pass transistor that is enabled (switched on) to electrically connect signal lines of the routing network. Each PIP typically has several inputs and several outputs. Some PIPs have as many as 20 combined ways of going into and out of the PIP. This means that each PIP can be used in any of several different routes through the switch matrix.
In a line segment between two flip-flops a first flip-flop is connected to a first PIP with a signal line (also known as a metal trace or “wire”), and the first PIP is connected to second PIP with another signal line and so forth until the final PIP in the line segment is connected to a second flip-flop. There are typically many possible routes between the first and second flip-flops, but one is configured by the user, or is automatically configured for the user, when the PLD is programmed. For purposes of discussion, the originally programmed line segment will be called the “original signal path.”
Occasionally, a PLD fails after it has been tested electrically. It is highly desirable to analyze a failed PLD to determine why the part failed. In some cases, the failure is due to a faulty line segment. A faulty line segment is identified using read-back capture techniques. After the faulty line segment is identified, the location of the faulty line segment on the silicon chip is determined from the manufacturing documentation, and the chip is physically deprocessed to microscopically examine each layer of the faulty line segment in the physical device to see if a fault can be identified. The fault might be a break in a wire trace, a shorted trace, or a high-resistive via, for example.
However, even if the failed line segment is identified, the fault is frequently not observed or observable. Furthermore, deprocessing the failed part, layer by layer, and visually inspecting the line segment after each step of removal is very time consuming and expensive.
Therefore, a fault isolation technique that more reliably identifies points of failure in a line segment is desirable.